For example, Japanese Patent Application Laid-open Publication No. 2009-110512 (hereinafter referred to as ‘PTL1’) discloses one example of network on chip architecture. The network on chip which is described in PTL1 includes integration processor blocks, a router, memory communication controllers and a network interface controller. In the network on chip described in PTL1, firstly, each of the integration processor blocks is coupled with the router through the memory communication controller and the network interface controller. Secondly, each of the memory communication controllers controls communication between the integration processor block and a memory. Thirdly, each of the network interface controllers controls communication between the integration processor blocks through the router.
Japanese Patent Application Laid-open Publication No. 2011-182393 (hereinafter referred to as ‘PTL2’) discloses an example of a chip using network on chip architecture. The chip which is described in PTL 2 includes function modules. Each of the function modules includes a single processing unit and a single routing unit connected to one another. Furthermore, connections called routing connection, each of which has at least one end connected to the routing unit of the function module, where the routing connections connect between themselves the routing units of the functional modules so as to allow a routing of data between the processing units of the functional modules. In the chip, firstly, the routing unit of at least one function modules, which are called split routing unit, includes two routers called a first-level router and a second-level router respectively. The first-level router and the second-level router are connected with each other. The first-level router is moreover connected to at least two routing connections. The second level router is moreover connected to the processing unit of the function module, and is also connected to at least another routing connection.